This exploded diagram reveals a further 64MiB of L3 cache atop the middle of the CCD, with structural silicon inserts to both facet of the brand new layer. [credit: AMD ]
Yesterday at Computex 2021, AMD CEO Lisa Su confirmed off the corporate’s subsequent huge efficiency play—3D stacked chiplets, permitting the corporate to triple the quantity of L3 cache on its flagship Zen three CPUs.
The expertise is simply what it appears like—a layer of SRAM cache sitting atop the Complicated Core Die (CCD) of the CPU itself. Present Zen three structure integrates 32MiB of L3 cache per eight-core chiplet—making 64MiB complete for a 12- or 16-core chiplet just like the Ryzen 9 5900X or 5950X. The brand new expertise provides a further 64MiB L3 cache on prime of every chiplet’s CCD, bonded with through-silicon vias (TSVs).
The extra 64MiB L3 cache layer doesn’t lengthen the width of the CCD, leading to a necessity for structural silicon to steadiness stress from the CPU cooling system. Compute and cache dies are each thinned within the new design, permitting it to share substrate and warmth spreader expertise with present Ryzen 5000 processors.
Learn four remaining paragraphs | Feedback